- Binding at compile time (absolute code), load time (relocatable code) or execution time (needs hardware: MMU).
- Logical (virtual) address: generated by the CPU. Physical address: seen by the memory unit. They differ under execution-time binding.
- MMU maps logical to physical at run time; simplest form adds the relocation (base) register.
🎯 How this can come up · 1 question
With relocation register 14000, logical address 346 maps to:
Correct: 14346.
- Swapping: move a process temporarily to a backing store and back. Transfer time dominates.
- Contiguous allocation: each process in one block; base + limit registers protect it.
- First fit: first hole big enough. Best fit: smallest hole big enough. Worst fit: largest hole.
🎯 How this can come up · 2 questions
Holes: 100, 500, 200, 300, 600 KB. Best fit places a 212 KB request in:
Correct: 300 KB.
Same holes; first fit places 212 KB in:
Correct: 500 KB.
- External fragmentation: enough total free memory but not contiguous (fix: compaction, paging). Internal: allocated block larger than requested.
🎯 How this can come up · 1 question
Paging eliminates:
Correct: External fragmentation.
- Segmentation: memory as a collection of variable-size segments (main, stack, symbol table…); logical address = <segment, offset>.
- Segment table has base and limit; offset d must be < limit, else trap. Physical = base + d.
- Segment-table exercise: check d < limit first, then add base.
🎯 How this can come up · 1 question
Segment 0 has base 219, limit 600. Translate (0, 430) and (0, 700).
(0, 430): 430 < 600 → physical 219 + 430 = 649. (0, 700): 700 ≥ 600 → addressing error (trap).
- Paging: physical memory split into fixed-size frames, logical memory into pages of the same size; a page table maps page → frame.
- Logical address = page number p (high m − n bits) + offset d (low n bits) for page size 2ⁿ and logical space 2ᵐ.
🎯 How this can come up · 1 question
With 4 KB pages, how many bits are the page offset?
2¹² = 4096.
- Exercise: logical space 256 pages × 4 KB = 2²⁰ → 20-bit logical address (8-bit page number + 12-bit offset).
🎯 How this can come up · 1 question
256 pages of 4 KB each need a logical address of:
8 + 12.
- Page table in memory (PTBR, PTLR) means two memory accesses per reference; the TLB (associative cache) fixes this.
- EAT = h·(TLB + memory) + (1 − h)·(TLB + 2·memory), with h the hit ratio.
🎯 How this can come up · 1 question
TLB 20 ns, memory 100 ns, hit ratio 80%. EAT =
0.8·120 + 0.2·220.
- Protection: a valid–invalid bit per page-table entry; also read/write/execute bits.
- Shared pages: one copy of read-only (reentrant) code mapped into several processes.
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