CS330 · Annotated SlidesChapter 8 — Memory Management
Chapter 8 · Annotated slides

Memory Management

Address binding, logical vs. physical addresses and the MMU, swapping, contiguous allocation (first, best and worst fit) and fragmentation, segmentation, paging and address translation, the TLB and effective access time, protection and shared pages.

Slide text Study notes Highlight: key words Tips, tricks & traps Seen again elsewhere How it can come up
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    In this lecture, we will discuss the following:

    • Background
    • Swapping
    • Contiguous Memory Allocation
    • Paging
    • Segmentation
    • Segmentation with Paging
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      • Program must be brought into memory and placed within a process for it to be executed.
      • A process may be moved between memory and disk during execution.
      • Main memory and registers are only storage CPU can access directly
      • Memory unit only sees a stream of addresses + read requests, or address + data and write requests
      • Input queue – collection of processes on the disk that are waiting to be brought into memory for execution.
      • User programs go through several steps before being executed.
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        Slide 4: Address binding of instructions and data to memory
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        1. Binding at compile time (absolute code), load time (relocatable code) or execution time (needs hardware: MMU).
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          1. Logical (virtual) address: generated by the CPU. Physical address: seen by the memory unit. They differ under execution-time binding.
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            1. MMU maps logical to physical at run time; simplest form adds the relocation (base) register.
            🎯 How this can come up · 1 question
            MCQ

            With relocation register 14000, logical address 346 maps to:

            • A process can be swapped temporarily out of memory to a backing store , and then brought back into memory for continued execution. (ex: Round Robin Algorithm)
            • Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images.
            • Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed.
            • Does the swapped out process need to swap back in to same physical addresses?
            • Depends on address binding method, if binding is done
              • At assembly or load time, p moves to the same location
              • At execution time, process can be swapped into diff memory space because physical add are computed during execution time
            • Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped.
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            1. Swapping: move a process temporarily to a backing store and back. Transfer time dominates.
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              Slide 11: ➢ If next processes to be put on CPU is not in memory, need to swap
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                Slide 12: ➢ Main memory must support both OS and user processes
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                1. Contiguous allocation: each process in one block; base + limit registers protect it.
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                  Slide 14: ➢ Multiple-partition allocation
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                    1. First fit: first hole big enough. Best fit: smallest hole big enough. Worst fit: largest hole.
                    🎯 How this can come up · 2 questions
                    MCQ

                    Holes: 100, 500, 200, 300, 600 KB. Best fit places a 212 KB request in:

                    MCQ

                    Same holes; first fit places 212 KB in:

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                        • External Fragmentation: Enough total memory space exists to satisfy a request, but it is not contiguous.
                          • Solutions
                            • Compaction- Shuffle memory contents to place all free memory together in one large block. If relocation is static and is done at assembly or load time, compaction cannot be done. It is possible only if relocation is dynamic and is done at execution time.
                            • Allow the logical-address space of a process to be noncontiguous. Ex: Paging and Segmentation
                        • Internal Fragmentation: when memory allocated is slightly larger than the size needed by the process. the size difference between the process size and the allocated memory is memory that is internal to a partition, but not being used.
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                        1. External fragmentation: enough total free memory but not contiguous (fix: compaction, paging). Internal: allocated block larger than requested.
                        Exam trapPaging has NO external fragmentation but can have internal fragmentation in the last page.
                        🎯 How this can come up · 1 question
                        MCQ

                        Paging eliminates:

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                          • Memory-management scheme that supports user view of memory.
                          • A logical address space is a collection of segments.
                          • A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, local variables, global variables, common block, stack, symbol table, arrays
                          • Each segment has a name and a length. For simplicity, the segments are given numbers.
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                          1. Segmentation: memory as a collection of variable-size segments (main, stack, symbol table…); logical address = <segment, offset>.
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                              1. Segment table has base and limit; offset d must be < limit, else trap. Physical = base + d.
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                                Slide 25: • Consider the following segment table:
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                                1. Segment-table exercise: check d < limit first, then add base.
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                                Written

                                Segment 0 has base 219, limit 600. Translate (0, 430) and (0, 700).

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                                  ➢ Paging allows the physical address space of a process to be non-

                                  contiguous

                                  • Paging relieves fragmentation issue. Single process can be distributed over a number of holes.
                                  • Divide physical memory into fixed-sized blocks called frames 1 (size is power of 2, between 512 bytes and GB per page).
                                  • Divide logical memory into blocks of same size called pages.
                                  • Keep track of all free frames.
                                  • To run a program of size N pages, need to find N free frames and load program.
                                  • Set up a page table to translate logical to physical addresses
                                  • Internal fragmentation
                                  ➢ Paging allows the physical address space of a process to be non-
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                                  1. Paging: physical memory split into fixed-size frames, logical memory into pages of the same size; a page table maps page → frame.
                                  Slide 28: ➢ Address generated by CPU is divided into:
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                                  1. Logical address = page number p (high m − n bits) + offset d (low n bits) for page size 2ⁿ and logical space 2ᵐ.
                                  🎯 How this can come up · 1 question
                                  MCQ

                                  With 4 KB pages, how many bits are the page offset?

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                                        • Consider a logical address space of 256 pages with a 4-KB page size, mapped onto a physical memory of 64 frames. a. How many bits are required in the logical address?
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                                        1. Exercise: logical space 256 pages × 4 KB = 2²⁰ → 20-bit logical address (8-bit page number + 12-bit offset).
                                        🎯 How this can come up · 1 question
                                        MCQ

                                        256 pages of 4 KB each need a logical address of:

                                        Consider that the physical memory is 256K, logical memory (per process) is 64K

                                        1.

                                        and the page size is 2K. Calculate the following values Number of pages per process

                                        a)

                                        Number of frames in physical memory

                                        b)

                                        Number of bits indicating page number

                                        c)

                                        Number of bits indicating offset

                                        d)

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                                            1. Page table in memory (PTBR, PTLR) means two memory accesses per reference; the TLB (associative cache) fixes this.

                                            • Associative registers Page # Frame # Address translation (page #, frame #)
                                              • If page# is in associative register, get frame # out.
                                              • Otherwise get frame # from page table in memory
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                                                ➢ Effective access time (EAT) is the average time needed to access

                                                memory.

                                                • Hit Ratio = h: The percentage of times that a particular page number is found in the TLB.
                                                • Effective access time can be calculated based on:
                                                  • The time it takes to access main memory
                                                  • The time it takes to access the TLB
                                                  • The hit ratio for the TLB
                                                • Example: Consider h = 80%,  = 20ns for TLB search, 100ns for memory access
                                                  • Time to access main memory = 100ns
                                                  • Time to access TLB = 20 ns
                                                  • Hit ratio = 0.8 (80%) we found the desired page No in the TLB 80% of time
                                                  • If page is found in TLB, total access time = 120?
                                                  • If page is not found in TLB, total access time = 220?need to access memory for page table & frame No(100) & access the desire byte in memory (100)
                                                  • Effective access time = ? 0.8 * 120 + 0.2 *220 = 140 ns where, h = hit ratio of TLB EAT = h*(c+m) + (1-h)*(c+2m) m = Memory access time c = TLB access time
                                                ➢ Effective access time (EAT) is the average time needed to access
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                                                1. EAT = h·(TLB + memory) + (1 − h)·(TLB + 2·memory), with h the hit ratio.
                                                🎯 How this can come up · 1 question
                                                MCQ

                                                TLB 20 ns, memory 100 ns, hit ratio 80%. EAT =

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                                                    • Memory protection in a paged environment is implemented by associating protection bit with each frame.
                                                    • Valid-invalid bit attached to each entry in the page table:
                                                      • valid indicates that the associated page is in the process logical “ ” ’ address space, and is thus a legal page .
                                                      • invalid indicates that the page is not in the process logical “ ” ’ address space.
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                                                    1. Protection: a valid–invalid bit per page-table entry; also read/write/execute bits.
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                                                      • Shared code
                                                        • One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems).
                                                        • Shared code must appear in same location in the logical address space of all processes.
                                                      • Private code and data
                                                        • Each process keeps a separate copy of the code and data.
                                                        • The pages for the private code and data can appear anywhere in the logical address space.
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                                                      1. Shared pages: one copy of read-only (reentrant) code mapped into several processes.
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